In the conventional semiconductor packages, a plurality of leads of leadframes have been widely implemented as chip carriers and as electrical media such as Thin Small Outline Package (TSOP), Lead-On-Chip (LOC) package, Chip-On-Lead package (COL) where chips are disposed on the leads of leadframes, then the chips and the leads of leadframes are encapsulated by an encapsulant. The leads of leadframes can replace die pads for die attachment. However, just using the leads of leadframes is not enough to support the chip leading to chip or lead shifting issues during molding.
Since the leads of leadframes are not strong enough to hold the chips during molding processes, the leads of leadframes are easy to shake or shift due to mold flow causing bonding wires, internal portions of leads, or chips exposed from the encapsulant leading to poor packaging yields. In order to reduce the undesired exposure of encapsulated components exposed from the encapsulant, the vertical distances from the leads of leadframes to top or bottom of encapsulant are increased leading to the increase of package thickness which can not be implemented for multi-chip stacking. Furthermore, as the frequencies or the powers of chips keep increasing, more heat is generated during operations. As the distances from the leads of leadframes to the encapsulant are increased, the corresponding heat resistivity will also increase which means heat generated by the chip can not easily dissipate outside the chip leading to chip failure.